Floating Point High Performance Low Area SFU
نویسندگان
چکیده
منابع مشابه
High-Performance Floating Point Divide
In modern processors floating point divide operations often take 20 to 25 clock cycles, five times that of multiplication. Typically multiplicative algorithms with quadratic convergence are used for high-performance divide. A divide unit based on the multiplicative Newton-Raphson iteration is proposed. This divide unit utilizes the higher-order Newton-Raphson reciprocal approximation to compute...
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ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2015
ISSN: 0974-5645,0974-6846
DOI: 10.17485/ijst/2015/v8i20/78367